1. Field of the Invention
The present invention relates to a method for manufacturing an article having a communicating hole. In addition, it relates to a method for manufacturing a semiconductor device by using a dual damascene process.
2. Description of the Related Art
Mostly, Cu has been used as a wiring material of semiconductor devices. However, it is difficult to transfer a pattern to Cu itself. Therefore, a damascene process, in particular a dual damascene process, in which a trench to be used for wiring or forming electrodes and a via are formed simultaneously, has been noted.
With respect to a method for manufacturing a semiconductor device by using this dual damascene process, a technology described in Japanese Patent Laid-Open No. 2004-221191 will be described.
In FIG. 9A, reference numeral 1901 denotes a Cu wiring, reference numeral 1902 denotes a SiC film, reference numeral 1903 denotes an organic low dielectric constant film, reference numeral 1904 denotes SiC, reference numeral 1905 denotes SiO2, and reference numeral 1906 denotes a resist mask provided with a pattern of a wiring trench.
As shown in FIG. 9B, SiO2 1905 is etched through the use of the resist mask 1906. As shown in FIG. 9C, a photosensitive resist is applied all over the surface, and exposure and development are performed, so that a resist mask 1910 provided with a pattern of a via hole is formed.
The SiO2 film 1905 and the SiC film 1904 are etched by using the resulting resist mask 1910 (FIG. 9D). Thereafter, by using the two-layer hard mask (1904 and 1905), the organic low dielectric constant film 1903 is etched and, simultaneously, the resist mask 1910 is removed (FIG. 9E).
The SiC film 1904 is etched by using the SiO2 film 1905 (FIG. 9F). Subsequently, the organic low dielectric constant film 1903 serving as an interlayer insulating film is etched by using the SiO2 film 1905 and the SiC film 1904 as masks.
In this manner, a wiring trench 1950 and a via hole 1935 are produced (FIG. 9G). Finally, the SiC film 1902 is removed by using the SiO2 film 1905 and the organic low dielectric constant film 1903 as masks (FIG. 9H). Subsequently, Cu is filled by plating into the wiring trench and the via hole, so that a dual damascene structure is produced.
In general, in the dual damascene process, a substrate layer made of a refractory metal, e.g., a barrier metal, and/or a refractory metal compound is formed in a trench to be used for wiring and a via hole and, thereafter, Cu, Al, an aluminum alloy, or the like is deposited.
Examples of deposition methods include a sputtering method, a CVD method, and if necessary, a process in which reflow is performed. The following removal of unnecessary Cu, Al, or the like can be performed not only by CMP, but also by physical removal, e.g., grinding and polishing, chemical etching, or the like.